AK8181C draft - e - 01 feb - 2013 - 1 - features two differential 3.3v lvpecl outputs selectable two lvttl/ lvcmos in puts clock output frequency up to 266 mhz o utput skew : 2 0ps max imum part - to - part skew : 2 0 0ps maximum propagation de l ay : 1.4 ns maximum a dditive phase jitter(rms) : 0.0 3 ps(typical) operating temperature range: - 4 0 to +85 package: 14 - pin tssop (pb free) pin compatible with ics8535 i - 2 1 description the ak8181 c is a member of akm lvpecl clock fanout buffer family design ed for telecom, networking and computer applications , requiring a ra nge of clocks with high performance and low skew . the AK8181C distributes 2 buffered clocks . AK8181C are derived f r o m akm long - term - experienced clock devic e technology , and enable clo ck output to perform low skew . the AK8181C is ava ilable in a 14 - pin tssop pa ckage. block diagram 3.3v lvpecl 1: 2 preliminary clock fanout buffer ak8181 c
AK8181C feb - 2013 draft - e - 01 - 2 - pin d escription s package: 14 - pin tsso p (top view) pwr: power pin, in: input pin, out: output pin pin no. pin name pin type pullup down description 1 vss pwr --- negative power supply 2 clk _en in pull up synchronizing clock output enable (lvcmos/lvttl) pin is connected to vdd by internal resistor. (typ. 51k ) high (open): clock outputs follow clock input. low: q outputs are forced low, qn outputs are forced high. 3 clk_sel in pull down clk select input (lvcmos/lvttl) pin is connected to vss by internal resistor. (typ. 51k ) high: selects clk1 input low ( open): selects clk0 input 4 clk0 in pull down lvcmos/lvttl clock input pin is connected to vss by internal resistor. (typ. 51k ) *when using clk1 input (clk_sel=high),it should be connected to vss or opened. 5 vss pwr --- negative power supply 6 clk1 i n pill down lvcmos/lvttl clock input pin is connected to vss by internal resistor. (typ. 51k ) *when using clk0 input (clk_sel=low), it should be connected to vss or opened. 7 vdd pwr --- positive power supply 8 vdd pwr --- positive power supply 9,10 q 1n, q1 out --- differential clock output (lvpecl) 11 nc --- --- no connect 12, 13 q0n, q0 out --- differential clock output (lvpecl) 14 vdd pwr --- positive power supply
AK8181C draft - e - 01 feb - 20 13 - 3 - abso lute maximum rating ov er operating free - air temperature range unless otherwise noted (1) items s ymbol ratings unit s upply v oltage ( 2 ) vdd - 0.3 to 4.6 v input voltage ( 2 ) vin - 0. 5 to vdd+0. 5 v input c urrent (any pins except supplies) i in 10 ma storage temperature tstg - 55 t o 15 0 ? c note (1) stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. f unctional operation of the device at these or any other conditions beyond those indicated under recom mended operating conditions is not implied. exposure to absolute - maximum - rating conditions for extended periods may affect device reliability. electrical par ameters are guaranteed only over the recommended operating temperature range. (2) vss =0v thi s device is manufactured on a cmos process, therefore, generically susceptible to damage by excessive static voltage. failure to observe proper handling and installation procedures can cause damage . akm recommends that this device is handled with appropri ate precautions. recommended operation condition s parameter s ymbol conditions m in typ m ax unit operating t emperature ta - 4 0 85 ? c supply voltage (1) vdd vdd ? 5%, vss=0v 3. 135 3.3 3. 465 v (1) power of 3.3v requires to be supplied from a single sourc e. a decoupling capacitor of 0.1 f for power supply line should be located close to each vdd pin. pin characteristics parameter s ymbol conditions m in typ m ax unit input capacitance c in 4 pf input pullup resistor r pu 51 k input pulldown resis tor r pd 51 k esd sensitive device
AK8181C feb - 2013 draft - e - 01 - 4 - dc characteristics all specifications at vdd= 3.3v ? 5%, vss=0v, ta: - 40 to +85 c , unless otherwise noted parameter symbol conditions min typ max unit i nput high v oltage v ih 2.0 vdd+0.3 v i nput low v oltage clk0, clk1 v il - 0.3 1.3 v clk_en, clk_sel - 0.3 0. 8 v input high c urrent clk0, clk1, clk_sel i h vin=vdd =3.465v 150 a a l vin=vss , vdd=3.465v - 5 a a (1) v oh vdd - 1.4 vdd - 0.9 v o utput low voltage (1) v ol vdd - 2.0 vdd - 1.7 v peak - to - peak output voltage swing v swing 0.6 1.0 v supply c urrent i dd 50 ma (1) outputs terminated with 50 to vdd - 2v. ac characteristics all specifications at vdd= 3.3 v ? 5%, vss=0v, ta: - 40 to +85 c , unless otherwise noted (1) measured from the vdd/2 of the input to the differential output crossing point. (2) defined as skew bet ween outputs at the same supply voltage and with equal load conditions. (3) this parameter is defined in accordance with jedec standard 65. (4) design value. (5) defined as skew between output s on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. parameter symbol conditions min typ max unit output frequency f out 266 mhz propagation delay (1) t pd 0.6 1.4 n s output skew (2)(3) t sk(o) 2 0 ps part - to - part skew (3 ) (5 ) t skpp 200 ps buffe r additive jitter, rms t jit 12khz to 20mhz @156.25mhz 0.0 3 ps output rise/fall time (4) t r , t f 20% to 80% 200 600 p s output duty cycle dc out 48 50 52 %
AK8181C draft - e - 01 feb - 20 13 - 5 - parameter measurement information figure 1 3.3v output load test circuit fi gure 2 part - to - part skew figure 3 output skew figure 4 output rise/fall time figure 5 propagation delay figure 6 output duty / pulse width/ period z o = 5 0 w 5 0 w z o = 5 0 w s c o p e 5 0 w - 1 . 3 v 0 . 1 6 5 v 2 . 0 v q x q x n q x t s k ( p p ) q x n q y n q y p a r t 2 p a r t 1 c l o c k o u t p u t s 8 0 % q x t s k ( o ) q x n q y n q y t r t f 2 0 % 8 0 % 2 0 % v s w i n g
AK8181C feb - 2013 draft - e - 01 - 6 - function table the following table shows the inputs/outputs clock state configured through the control pins. table 1 : control input function table inputs outpu ts clk_en clk_sel selected source q0, q 1 q0 n, q 1 n 0 0 (open) clk0 disabled: low disabled: high 0 1 clk1 disabled: low disabled: high 1 (open) 0 (open) clk0 enabled enabled 1 (open) 1 clk1 enabled enabled after clk_en switches, the clock outputs ar e disabled or enabled following a rising and falling input clock edge as shown in figure 7. in the active mode, the state of the outputs are a function of the clk0 and clk1 inputs as described in table 2. figure 7 clk_en timing diagram table 2 clock input function table inputs outputs clk0 or clk1 q0 , q 1 q0n , q 1 n 0 low high 1 high low c l k 0 , c l k 1 c l k _ e n q 0 n : q 3 n q 0 : q 3 d i s a b l e d e n a b l e d
AK8181C draft - e - 01 feb - 20 13 - 7 - package information ? mechanical data : 14 pin tssop ? marking ? rohs compliance all integ rated circuits form asahi kasei m icrodevices corporation (akm) assembled in lead - free packages* are fully compliant with rohs. (*) rohs compliant products from akm are identified with pb free letter indication on product label posted on the anti - shie ld bag and boxes. a: #1 pin index b: part number c: d ate code ( 7 digits) 1 14 7 8 ak 8 181 c xxxxx xx a b c preliminary
AK8181C feb - 2013 draft - e - 01 - 8 - important notice ? these products and their specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. ? descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related in formation in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or o ther rights in the application or use of such information contained herein. ? any export of these products, or devices or sy stems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor autho rized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fiel ds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the responsibility of the buyer or distributor of akm products, who distributes, disposes o f, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
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